Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique

Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS) Technology roadmap. Despite the attractive opportunity that offers their organization onto regular crossbars, the problem of designing the nanowire decoder is still challenging and highly dependent on the nanowire fabrication technology. In this paper, we introduce a novel design style and encoding scheme for decoding nanowires fabricated with the Multi-Spacer-Patterning Technique (MSPT); and we present a method based on Gray codes that reduces the fabrication cost and improves the decoder reliability. We show that by arranging the code in a Gray code fashion, we decrease the fabrication complexity by 17% and the variability by 18% on average. By optimizing the decoder parameters, the simulations showed an improvement of the crossbar yield by 40% and a reduction of the effective bit area by 51% to 169 nm2

Complete Nanowire Crossbar Framework Optimized for the Multi-Spacer Patterning Technique

Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this paper, we propose for the first time the utilization of the multi-spacer patterning technique to fabricate nanowire crossbars with a high cross-point density up to 1010 cm−2. We propose a novel decoder fabrication method that can be included in a process dedicated to the multi-spacer patterning technique. We address the technology problems consisting in the variability and fabrication complexity at the design level by optimizing the encoding scheme. We show an overall reduction of the variability by 18% and a cancelation of the fabrication complexity overhead

Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays

We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer scale lithography and conventional fabrication techniques. It is shown that demonstrator Schottky Barrier (SB) devices fabricated with Cr/NiCr contacts present good subthreshold slope (70mV/dec), ION/IOFF ratio $>= 10^4$ and reproducible ambipolar behavior

Characterization of Memristive Poly-Si Nanowires via Empirical Physical Modelling

Memristors are passive circuit elements that behave as resistors with memory. The recently illustrated experimental realization of memristive behaviour of Polysilicon Nanowires has triggered interest in this concept, which is promising to a wide variety of application areas that include neuromorphic circuits. In order to progress with practical implementations that use this technology we need to expand our understanding of the conduction mechanisms in these structures and of the underlying relationship between device behavior and process manufacturing parameters. In this paper we explore these mechanisms through detailed simulation, which includes model calibration and correlation with experimental results. Through fitting of the test results we identify a unique set of density of states that characterize the particular technology implemented

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuitry that is defined on the lithography scale. In this paper, we evaluate the addressing scheme of the decoder circuit for NW crossbar arrays, based on the existing technological solutions for threshold voltage differentiation of NW devices. This is equivalent to using a multivalued logic addressing scheme. With this approach, it is possible to reduce the decoder size and keep it defect tolerant. We formally define two types of multivalued codes (i.e., hot and reflexive codes), and we estimate their yield under high variability conditions. Multivalued hot decoders yield better area saving than n-ary reflexive codes, and under severe conditions, reflexive codes enable a nonvanishing part of the code space to randomly recover. The choice of the optimal combination of decoder type and logic level saves area up to 24%. We also show that the precision of the addressing voltages when a high variability affects the threshold voltages is a crucial parameter for the decoder design and permits large savings in memory area. Moreover, a precise knowledge about the variability level improves the design of memory decoders by giving the right optimal code

Improving the fault tolerance of nanometric PLA designs

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric filaments such as Silicon NanoWires (SiNWs) and Carbon NanoTubes (CNTs). However, chips leveraging these nanoscale structures are expected to be affected by a large amount of manufacturing faults, way beyond what chip architects have learned to counter. In this paper, we show a design flow, based on software mapping algorithms, to improve the yield of nanometric Programmable Logic Arrays (PLAs). While further improvements to the manufacturing technology will be needed to make these devices fully usable, our flow can significantly shrink the gap between current and desired yield levels. Also, our approach does not need post-fabrication functional analysis and mapping, therefore dramatically cutting on verification costs. We check PLA yields by means of an accurate analyzer after Monte Carlo fault injection. We show that, compared to a baseline policy of wire replication, we achieve equal or better yields (8 % over a set of designs) depending on the underlying defect assumptions. 1